A 1 GIPS 1 W single-chip tightly-coupled four-way multiprocessor with architecture support for multiple control flow execution

Author

Nishi, N. ; Inoue, Takeru ; Nomura, M. ; Matsushita, S. ; Torii, S. ; Shibayama, A. ; Sakai, J. ; Ohsawa, T. ; Nakamura, Y. ; Shimada, S. ; Ito, Y. ; Edahiro, M. ; Mizuno, M. ; Minami, K. ; Matsuo, O. ; Inoue, H. ; Manabe, T. ; Yamazaki, T. ; Nakazawa, Y.

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

2000

fDate

9-9 Feb. 2000

Firstpage

418

Lastpage

419

Abstract

A 125 MHz 1 GIPS at 1.3 V 1 W microprocessor with single-chip tightly-coupled multiprocessor architecture and low-voltage circuits is targeted to high-performance and low-power embedded systems, especially smart information terminals. This paper shows an entire chip diagram integrating four tightly-coupled processors. Each processing element (PE) is in-order two-way issue superscalar with two ALU pipelines. A power-management unit (PMU) cuts off the leakage current of each power-control domain independently using dedicated power switches.

Keywords

embedded systems; low-power electronics; microprocessor chips; multiprocessing systems; 1 GIPS; 1 W; 1.3 V; 125 MHz; ALU pipeline; leakage current; low-power embedded system; low-voltage circuit; microprocessor; multiple control flow execution; power management unit; single-chip tightly-coupled multiprocessor architecture; smart information terminal; superscalar processing element; Automatic control; Buffer storage; Control systems; Data mining; Microprocessors; National electric code; Pollution; Registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State Circuits Conference, 2000. Digest of Technical Papers. ISSCC. 2000 IEEE International

Conference_Location

San Francisco, CA, USA

ISSN

0193-6530

Print_ISBN

0-7803-5853-8

Type

conf

DOI

10.1109/ISSCC.2000.839841

Filename

839841