VLSI implementation of fractional motion estimation interpolation for high efficiency video coding

Interpolation plays a key role in the fractional motion estimation (FME) of video encoders. A hardware implementation of a FME interpolator is presented for high efficiency video coding. The proposed interpolator processes each 8 × 8 block in a pipelined manner with efficiently shared finite impulse response filters to improve the performance while reducing gate counts. Implementation results show that the proposed design leads to fewer execution cycles with a small silicon area compared with conventional designs.