• DocumentCode
    1970155
  • Title

    Implementation of a redundant binary input acceptable multiplier

  • Author

    Wang, Guoping

  • Author_Institution
    Purdue Univ., Fort Wayne
  • fYear
    2007
  • fDate
    17-20 May 2007
  • Firstpage
    323
  • Lastpage
    326
  • Abstract
    A multiplier which can accept redundant binary number inputs is proposed using available unsigned multiplier (array multiplier, carry-save-addition tree multiplier, or multiplier using redundant binary representations). The proposed multiplier is applicable in redundant binary ALU unit or redundant binary processor.
  • Keywords
    digital signal processing chips; logic arrays; multiplying circuits; redundant number systems; ALU; arithmetic logic unit; array multiplier; available unsigned multiplier; carry-save-addition tree multiplier; redundant binary input acceptable multiplier; redundant binary processor; redundant binary representations; Arithmetic; Design methodology; Logic; USA Councils;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Electro/Information Technology, 2007 IEEE International Conference on
  • Conference_Location
    Chicago, IL
  • Print_ISBN
    978-1-4244-0941-9
  • Electronic_ISBN
    978-1-4244-0941-9
  • Type

    conf

  • DOI
    10.1109/EIT.2007.4374437
  • Filename
    4374437
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1970155