Memory arbitration and cache management in stream-based systems

With the ongoing advancements in VLSI technology the performance of an embedded system is determined to a large extent by the communication of data and instructions. This results in new methods for on- and off-chip communication and caching schemes. In this paper we use an arbitration scheme that exploits the characteristics of continuous `media´ streams while minimizing the latency for random (e.g. CPU) memory accesses to background memory. We also introduce a novel caching scheme for a stream-based multiprocessor architecture, to limit as much as possible the amount of on-chip buffering required to guarantee the throughput of the continuous streams. With these two schemes we can build an architecture for media processing with optimal flexibility at run-time while performance guarantees can be determined at compile-time