1970466

New polysilicon disposable sidewall process for sub-50 nm CMOS

Lee, K.L. ; Boyd, D. ; Brancaccio, J. ; Bucchignano, J. ; Cai, J. ; Chan, K. ; Hanafi, H. ; Kozlowski, P. ; Miller, R. ; Roy, R. ; Shi, L. ; Sikorski, E. ; Surendra, M. ; Wind, S. ; Yang, Q. ; Yoon, J. ; Yu, C. ; Zhang, Y. ; Taur, Y.

IBM Thomas J. Watson Research Center, Yorktown Heights, USA

2001

11-13 September 2001

159

162

Annealing; Boron; CMOS process; Chemical vapor deposition; Doping; Etching; Implants; Microelectronics; Strips;

English

ieee

Solid-State Device Research Conference, 2001. Proceeding of the 31st European

2-914601-01-8

conf

10.1109/ESSDERC.2001.195225

1506607