Title :
Innovative Scaling Method to Minimize Cost of Integrated Circuit Packages and Devices
Author :
Bhattacharyya, Bidyut K. ; Laskar, Nivedita ; Debnath, Shoubhik ; Baral, Debasis
Author_Institution :
Intel, Santa Clara, CA, USA
Abstract :
In this paper, we have shown an analytical technique to scale the power delivery solutions for a given integrated circuit (IC) chip that can draw currents to cause enough inductive noise for the IC to fail. This scaling method will also provide the optimum package solutions to minimize the cost of IC products. This method can be very useful to determine the package and die design methodology at the initial phase of the design cycle of the chip.
Keywords :
cost reduction; integrated circuit noise; integrated circuit packaging; IC chip; IC products; cost minimization; die design methodology; inductive noise; innovative scaling method; integrated circuit packages; optimum package solutions; power delivery solutions; Capacitance; Clocks; Inductance; Noise; Power supplies; Resistance; Silicon; (L) , (C) , and (R) of packages; Die decoupling capacitance; L, C, and R of packages; die decoupling resistance; organic land grid array core/coreless packages; power and ground noises; power deliver network (PDN);
Journal_Title :
Components, Packaging and Manufacturing Technology, IEEE Transactions on
DOI :
10.1109/TCPMT.2014.2339272
