Title :
Built-in generation of weighted test sequences for synchronous sequential circuits
Author :
Pomeranz, Irith ; Reddy, Sudhakar M.
Author_Institution :
Dept. of Electr. & Comput. Eng., Iowa Univ., Iowa City, IA, USA
Abstract :
We describe a method for on-chip generation of weighted test sequences for synchronous sequential circuits. For combinational circuits, three weights, 0, 0.5 and 1, are sufficient to achieve complete coverage of stuck-at faults, since these weights are sufficient to reproduce any specific test pattern. For sequential circuits, the weights we use are defined based on subsequences of a deterministic test sequence. Such weights allow us to reproduce parts of the test sequence, and help ensure that complete fault coverage would be obtained by the weighted test sequences generated
Keywords :
automatic test pattern generation; built-in self test; integrated circuit testing; integrated logic circuits; logic testing; sequences; sequential circuits; built-in generation; deterministic test sequence; fault coverage; onchip generation; subsequences; synchronous sequential circuits; weighted test sequences; Circuit faults; Circuit testing; Cities and towns; Combinational circuits; Delay; Electrical fault detection; Fault detection; Sequential analysis; Sequential circuits; Synchronous generators;
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
DOI :
10.1109/DATE.2000.840287
