DocumentCode :
1970905
Title :
NOVA interconnect for dynamically reconfigurable NoC systems
Author :
Vallina, Fernando Martinez ; Jachimiec, Nathan ; Saniie, Jafar
Author_Institution :
Illinois Inst. of Technol., Chicago
fYear :
2007
fDate :
17-20 May 2007
Firstpage :
546
Lastpage :
550
Abstract :
Network on a chip (NoC) topologies for interconnect offer the possibility of increasing the flexibility and performance of an embedded computational platform. NoC is also an enabling factor for the creation of dynamically reconfigurable single chip systems. In this paper, the NOVA interconnect topology is shown. NOVA is a hybrid topology for NoC interconnect targeted at an FPGA. This topology is able to efficiently support the communication workloads associated with multiprocessor, multi peripheral and reconfigurable systems. This paper presents simulation results on the performance and scalability of NOVA. Also, the performance of NOVA is compared to the star, torus, and hypercube topologies, and is shown to outperform these topologies.
Keywords :
field programmable gate arrays; network-on-chip; FPGA; NOVA interconnect topology; NoC systems; field programmable gate arrays; multiprocessor; network-on-chip; single chip systems; Computer networks; Costs; Degradation; Delay; Integrated circuit interconnections; Monitoring; Network topology; Network-on-a-chip; Scalability; System-on-a-chip;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electro/Information Technology, 2007 IEEE International Conference on
Conference_Location :
Chicago, IL
Print_ISBN :
978-1-4244-0941-9
Electronic_ISBN :
978-1-4244-0941-9
Type :
conf
DOI :
10.1109/EIT.2007.4374481
Filename :
4374481
Link To Document :
بازگشت