DocumentCode :
1970946
Title :
Meeting delay constraints in DSM by minimal repeater insertion
Author :
Liu, I-Min ; Aziz, Adnan ; Wong, D.F.
Author_Institution :
Dept. of Electr. & Comput. Eng., Texas Univ., Austin, TX, USA
fYear :
2000
fDate :
2000
Firstpage :
436
Lastpage :
440
Abstract :
We address the problem of inserting repeaters, selected from a library, at feasible locations in a placed and routed network to meet user-specified delay constraints for deep submicron (DSM) technology. We use minimal repeater area by taking advantage of slacks available in the network. Specifically, we transform the problem into an unconstrained optimization problem and solve it by iterative local refinement. We show that the optimal repeater locations and sizes that locally minimize the objective function in the unconstrained problem can be efficiently computed. We have implemented our algorithm and tested it on a set of benchmarks; experimental results are promising
Keywords :
VLSI; circuit layout CAD; circuit optimisation; delays; digital integrated circuits; high level synthesis; iterative methods; network routing; deep submicron technology; iterative local refinement; minimal repeater insertion; objective function minimisation; optimal repeater locations; optimal repeater sizes; placed/routed network; repeater area minimisation; unconstrained optimization problem; user-specified delay constraints; Delay effects; Electronic switching systems; Inductance; Integrated circuit noise; Read only memory; Repeaters; Routing; Very large scale integration; Wire; Wiring;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Design, Automation and Test in Europe Conference and Exhibition 2000. Proceedings
Conference_Location :
Paris
Print_ISBN :
0-7695-0537-6
Type :
conf
DOI :
10.1109/DATE.2000.840307
Filename :
840307
Link To Document :
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