Implementation of AES as a CMOS core

Rijndael is the new advanced encryption standard (AES) that was chosen by the American National Institute of Standards and Technology (NIST) in October 2000. This paper investigates the implementation of the 128 bits key size AES algorithm using an iterative architecture in a 0.18 micron semi-custom ASIC using a CMOS standard cell library. Our research focuses on the basic electronic codebook (ECB) mode. The circuit was efficiently designed to have both encryption and decryption functions. Depending on the input control signal, the design can work as an encryption core or a decryption core. Our result shows that, for a clock frequency of 100 MHz, we can achieve a throughput of more than 1 Gbps. The core area is approximately 2.6 mm². This high-speed hard macro can be used as a reusable IP block to be embedded into a system-on-chip (SOC) design in the future.