Title :
A versatile signed array multiplier suitable for VLSI implementation
Author :
Wang, Qi ; Shayan, Yousef R.
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
The basic building block of DSP-based implementation is multipliers. There are many multiplier structures suitable for VLSI implementation. In this paper, a new structure is proposed for 2´s complement multiplication and compared with other multiplier structures. It is shown that this proposed scheme has a more versatile and modular structure. Therefore, no redesign is required for different lengths of multipliers and few different types of cells are needed. Moreover, this new structure can be applied to booth-encoded partial products.
Keywords :
VLSI; multiplying circuits; trees (mathematics); 2s complement multiplication; DSP-based implementation; VLSI implementation; booth-encoded partial products; multipliers; very large scale integration; Delay effects; Digital signal processing; Logic arrays; Very large scale integration;
Conference_Titel :
Electrical and Computer Engineering, 2003. IEEE CCECE 2003. Canadian Conference on
Print_ISBN :
0-7803-7781-8
DOI :
10.1109/CCECE.2003.1226377
