Hardware algorithm for variable precision multiplication on FPGA

A hardwired algorithm for computing the variable precision multiplication is presented in this paper. The computation method is based on the use of a parallel multiplier of size m to compute the multiplication of two numbers of n times m bits. These numbers are represented in the variable precision floating point format, but in this work only the mantissas are considered; the exponents are easily obtained by adding the exponents of the two operands to be multiplied. In this computing method of multiplication, the partial products are added as soon as they are computed, resulting in the use of the lowest memory for intermediate results storage, (i.e. the size of the result is of 2n times m bits). The Xilinx FPGA circuits, of Virtex-II families and bigger ones, have interesting resources such as embedded multipliers 18 times 18 bits, memory blocks (SelectRam) and carry chain paths for the carry propagation acceleration and DCM blocks (digital clock manager) to generate and control clocks. These resources have been advantageously used, in the implementation, to reduce the computation delay compared to the solution that uses only FPGA CLBs (configurable logic blocks). Our architecture has been tailored to use these efficient resources and the resulting architecture is dedicated to compute the multiplication of operands of sizes ranging from 1 times 64 bits to 64 times 64 bits with a cycle time of 33 ns.