A 7b 1GS/s 60mW folding ADC in 65nm CMOS

Author

Lee, Jungho ; Michael, B.C. ; Park, Ho-Jin ; Park, Byeong-Ha

Author_Institution

Syst. LSI Div., Samsung Electron., Beijing, China

fYear

2010

fDate

22-23 Nov. 2010

Firstpage

338

Lastpage

341

Abstract

A 7b 1GS/s CMOS folding ADC is presented. It utilizes improved track-and-hold circuit using simple clock generator and bootstrapped sampling switch, sequential amplifier settling method in amplifier chain. It also uses low-power thermometer-to-binary encoder realized with transmission gate multiplexer and intermediate track-and-hold circuit for high-speed mediumresolution A/D conversion. The proposed ADC achieves about 6.5 effective bits for 250MHz input at 1GS/s. It consumes 60mW from 1.2V single supply. It is fabricated with 65nm LP CMOS process occupying 0.2mm² active area.

Keywords

CMOS digital integrated circuits; analogue-digital conversion; low-power electronics; sample and hold circuits; LP CMOS process; amplifier chain; bootstrapped sampling switch; clock generator; folding ADC; frequency 250 MHz; high-speed medium resolution A-D conversion; intermediate track-and-hold circuit; low-power thermometer-to-binary encoder; power 60 mW; sequential amplifier settling method; size 65 nm; transmission gate multiplexer; voltage 1.2 V; CMOS integrated circuits; Capacitors; Clocks; Interpolation; Logic gates; Power demand; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2010 International

Conference_Location

Seoul

Print_ISBN

978-1-4244-8633-5

Type

conf

DOI

10.1109/SOCDC.2010.5682901

Filename

5682901