Title :
A 6b 1.4GS/s 11.9mW 0.11mm2 65nm CMOS DAC with a 2-D INL bounded switching scheme
Author :
Kwon, Yi-Gi ; Lee, Seung-Hoon ; Jeon, Young-Deuk ; Kwon, Jong-Kee
Author_Institution :
Dept. of Electron. Eng., Sogang Univ., Seoul, South Korea
Abstract :
This work describes a 6b 1.4 GS/s 65 nm CMOS DAC based on a current cell matrix with a 2-D INL bounded switching scheme. The proposed switching scheme reduces current matching errors in both row and column lines with a simple row-column decoder. The proposed area-efficient deglitching circuit minimizes the timing error of each current cell and reduces the required number of transistors by 40% compared to the conventional master-slave deglitching circuits. The prototype DAC with an active die area of 0.11 mm2 shows an SFDR of 40.8 dB and consumes 11.9 mW at 1.0V and 1.4 GS/s.
Keywords :
CMOS analogue integrated circuits; CMOS digital integrated circuits; digital-analogue conversion; low-power electronics; switching circuits; timing circuits; 2D INL bounded switching scheme; CMOS DAC; SFDR; area-efficient deglitching circuit; current cell matrix; current matching error; digital-to-analog converter; integral nonlinearity bounded switching; power 11.9 mW; row-column decoder; size 65 nm; timing error; voltage 1 V; CMOS integrated circuits; Computer architecture; Decoding; Microprocessors; Prototypes; Switches; Switching circuits; 2-D INL bounded switching; CMOS; DAC; master-slave deglitching;
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
DOI :
10.1109/SOCDC.2010.5682937
