A 160MHz 4-bit pipeline multiplier using charge recovery logic technology

Author

Zhang, Yimeng ; Okamura, Leona ; Wang, Nan ; Yoshihara, Tsutomu

Author_Institution

Grad. Sch. of Inf., Production & Syst., Waseda Univ., Kitakyushu, Japan

fYear

2010

fDate

22-23 Nov. 2010

Firstpage

127

Lastpage

130

Abstract

In this paper a 4-bit pipeline multiplier is designed using a novel charge-recovery logic technology called Pulse Boost Logic (PBL), and fabricated out with Rohm 0.18μm CMOS process. Cadence Spectre simulation indicates that energy dissipation of proposed PBL multiplier is 79% of Enhanced Boost Logic with almost the same number of transistors. The test chip is using a LC resonant system for AC power supply, since PBL structure requires two phase non-overlap clock as power supply. The measurement result shows that operation frequency of PBL 4-bit pipeline multiplier is up to 161MHz, while the energy dissipation is 4.81pJ/cycle.

Keywords

CMOS logic circuits; clocks; logic circuits; logic design; multiplying circuits; AC power supply; CMOS process; LC resonant system; PBL multiplier; PBL structure; cadence spectre simulation; charge recovery logic technology; energy dissipation; enhanced boost logic; frequency 160 MHz; operation frequency; pipeline multiplier; pulse boost logic; size 0.18 mum; test chip; two phase nonoverlap clock; word length 4 bit; Clocks; Converters; Energy dissipation; Frequency measurement; Logic gates; Pipelines; Power supplies;

fLanguage

English

Publisher

ieee

Conference_Titel

SoC Design Conference (ISOCC), 2010 International

Conference_Location

Seoul

Print_ISBN

978-1-4244-8633-5

Type

conf

DOI

10.1109/SOCDC.2010.5682955

Filename

5682955