Title :
A synthesizable AXI protocol checker for SoC integration
Author :
Chen, Chien-Hung ; Ju, Jiun-Cheng ; Huang, Jer
Author_Institution :
Dept. of Comput. Sci. & Eng., Nat. Sun Yat-Sen Univ., Kaohsiung, Taiwan
Abstract :
System-on-a-Chip (SoC) design has become more and more complexly. Because difference functions components or IPs (Intellectual Property) will be integrated within a chip. The challenge of integration is “how to verify on-chip communication properties”. Although traditional simulation-based on-chip bus protocol checking bus signals to obey bus transaction behavior or not, however, they are still lack of a chip-level dynamic verification to assist hardware debugging. We proposed a rule-based synthesizable AMBA AXI protocol checker. The AXI protocol checker contains 44 rules to check on-chip communication properties accuracy. In the verification strategy, we use the Synopsys VIP (Verification IP) to verify AXI protocol checker. In the experimental results, the chip cost of AXI protocol checker is 70.7 K gate counts and critical path is 4.13 ns (about 242 MHz) under TSMC 0.18 um CMOS 1P6M Technology.
Keywords :
CMOS integrated circuits; electronic engineering computing; formal verification; logic design; system-on-chip; CMOS 1P6M technology; SoC integration; chip-level dynamic verification; hardware debugging; intellectual property; rule-based synthesizable AMBA AXI protocol checker; synopsys VIP; system-on-a-chip; verification IP; Computational modeling; Computer architecture; Debugging; IP networks; Monitoring; Protocols; System-on-a-chip; AMBA AXI; Protocol Checking; Rule-based; VIP; debugging;
Conference_Titel :
SoC Design Conference (ISOCC), 2010 International
Conference_Location :
Seoul
Print_ISBN :
978-1-4244-8633-5
DOI :
10.1109/SOCDC.2010.5682961