DocumentCode
1976265
Title
Benes switching fabrics with O(N)-complexity internal backpressure
Author
Sapountzis, Georgios ; Katevenis, Manolis
Author_Institution
Inst. of Comput. Sci., Found. for Res. & Technol. Hellas, Heraklion, Greece
fYear
2003
fDate
24-27 June 2003
Firstpage
11
Lastpage
16
Abstract
Multistage buffered switching fabrics are the most efficient method for scaling packet switches to very large numbers of ports. The Benes network is the lowest-cost switching fabric known to yield operation which is free of internal blocking. Backpressure inside a switching fabric can limit the use of expensive off-chip buffer memory to just virtual-output queues (VOQ) in front of the input stage. The paper extends the known backpressure architectures to the Benes network. To achieve this, we had to combine per-flow backpressure, multipath routing (inverse multiplexing), and cell resequencing successfully. We present a flow merging scheme that is needed to bring the cost of backpressure down to O(N) per switching element. We prove freedom from deadlock for a wide class of multipath cell distribution algorithms. Using a cell-time-accurate simulator, we verify that operation is free of internal blocking, we evaluate various cell distribution and resequencing methods, we compare performance to that of ideal output queueing and the iSLIP crossbar scheduling algorithm, and we show that the delay of well-behaved flows remains unaffected by the presence of congested traffic to oversubscribed output ports.
Keywords
buffer storage; delays; electronic switching systems; multipath channels; multistage interconnection networks; packet switching; queueing theory; scheduling; telecommunication network routing; Benes network; VLSI technology; VOQ; backpressure architectures; buffer memory; cell resequencing; congested traffic; crossbar scheduling algorithm; iSLIP scheduling algorithm; inverse multiplexing; multipath routing; multistage buffered switching fabrics; packet switches; virtual-output queues; Costs; Delay; Fabrics; Merging; Packet switching; Routing; Scheduling algorithm; Switches; System recovery; Traffic control;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Switching and Routing, 2003, HPSR. Workshop on
Print_ISBN
0-7803-7710-9
Type
conf
DOI
10.1109/HPSR.2003.1226672
Filename
1226672
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