Title :
A 42.5 mm2 1 Mb nonvolatile ferroelectric memory utilizing advanced architecture for enhanced reliability
Author :
Kraus, William ; Lehman, Lark ; Wilson, Dennis ; Yamazaki, Tsutomu ; Ohno, Chikai ; Nagai, Eiichi ; Yamazaki, Hiroshi ; Suzuki, Hideaki
Author_Institution :
Ramtron Int. Corp., Colorado Springs, CO, USA
Abstract :
A 1 Mb ferroelectric random access memory (FRAM(R)) with 15.8 μm2 cell size and 60 ns read/write times incorporates a one transistor-one capacitor (ITIC) architecture. Data retention reliability is improved by the use of a pre-charged ferroelectric capacitor reference, an in-pitch ferroelectric capacitor circuit for wordline boosting, and an optimized sensing scheme. Active power is 50 mW at 5.0 V. PZT capacitors are used with a 0.5 μm CMP planarized CMOS process
Keywords :
CMOS memory circuits; chemical mechanical polishing; circuit optimisation; ferroelectric capacitors; ferroelectric storage; integrated circuit design; integrated circuit reliability; memory architecture; random-access storage; 0.5 micron; 1 Mbit; 5 V; 50 mW; 60 ns; CMP planarized CMOS process; FRAM; ITIC architecture; PZT; PZT capacitors; PbZrO3TiO3; Si; SiO2-Si; active power; cell size; data retention reliability; ferroelectric random access memory; in-pitch ferroelectric capacitor circuit; memory architecture; nonvolatile ferroelectric memory; one transistor-one capacitor architecture; optimized sensing scheme; pre-charged ferroelectric capacitor reference; read/write times; reliability; wordline boosting; Boosting; Capacitors; Circuit noise; Driver circuits; Electrodes; Ferroelectric materials; Memory architecture; Nonvolatile memory; Polarization; Timing;
Conference_Titel :
Nonvolatile Memory Technology Conference, 1998. 1998 Proceedings. Seventh Biennial IEEE
Conference_Location :
Albuquerque, NM
Print_ISBN :
0-7803-4518-5
DOI :
10.1109/NVMT.1998.723210
