Scaling of high-k/metal-gate Trigate SOI nanowire transistors down to 10nm width

Author

Coquand, R. ; Barraud, S. ; Cassé, M. ; Leroux, P. ; Vizioz, C. ; Comboroure, C. ; Perreau, P. ; Ernst, E. ; Samson, M.-P. ; Maffini-Alvaro, V. ; Tabone, C. ; Barnola, S. ; Munteanu, D. ; Ghibaudo, G. ; Monfray, S. ; Boeuf, F. ; Poiroux, T.

Author_Institution

CEA-LETI, MINATEC, Grenoble, France

fYear

2012

fDate

6-7 March 2012

Firstpage

37

Lastpage

40

Abstract

In this paper, Tri-Gate Nanowire (TGNW) FETs with high-k/metal gate are studied as an alternative way to planar devices for the future CMOS technological nodes (14 nm and beyond). The influence of Si film thickness (H) and nanowire width (W) on electrical performances of long- and short-channel devices are presented and discussed. We show that the transport properties in our TGNW are fully governed by the additive contributions of the (100) top surface and (110) sidewalls. As compared to wide planar devices, the improvement of electrostatic integrity (SS and DIBL) of scaled down TGNW FET is clearly demonstrated.

Keywords

CMOS integrated circuits; field effect transistors; nanowires; silicon-on-insulator; CMOS technological nodes; FET; TGNW; high-k/metal-gate trigate SOI nanowire transistors; Electrostatics; FETs; Logic gates; MOS devices; Metals; Silicon; Very large scale integration; Carrier mobility; Scalability; Tri-Gate SOI Nanowire;

fLanguage

English

Publisher

ieee

Conference_Titel

Ultimate Integration on Silicon (ULIS), 2012 13th International Conference on

Conference_Location

Grenoble

Print_ISBN

978-1-4673-0191-6

Electronic_ISBN

978-1-4673-0190-9

Type

conf

DOI

10.1109/ULIS.2012.6193351

Filename

6193351