Author :
Sklénard, B. ; Xu, C. ; Batude, P. ; Previtali, B. ; Tabone, C. ; Rafhay, Q. ; Colombeau, B. ; Khaja, F.-A. ; Martín-Bragado, I. ; Berthoz, J. ; Allain, F. ; Toffoli, A. ; Kies, R. ; Jaud, M.-A. ; Rivallin, P. ; Cristoloveanu, S. ; Tavernier, C. ; Faynot,
Abstract :
In this paper, we demonstrate low junction leakage for devices fabricated at low temperature (≤ 650°C). This is explained by the reduced channel thickness of our device (6 nm). We show this through both experimental data and KMC simulations that enable to understand the origin of the leakage reduction.
Keywords :
MOSFET; Monte Carlo methods; elemental semiconductors; leakage currents; silicon; silicon-on-insulator; FDSOI device; KMC simulation; MOSFET; Si; channel thickness reduction; fully-depleted SOI device; kinetic Monte Carlo simulation; leakage current; low junction leakage reduction; low temperature processing; size 6 nm; Annealing; Films; Implants; Junctions; Logic gates; Silicon; Silicon on insulator technology; 3D sequential integration; EOR defects; Fully-depleted SOI (FDSOI); SPE; low temperature processes;
