• DocumentCode
    1979204
  • Title

    A very compact 1MS/s Nyquist-rate A/D-converter with 12 effective bits

  • Author

    Rombouts, Pieter ; Woestyn, Pierre ; De Bock, Maarten ; Raman, Johan

  • Author_Institution
    Elektronics & Inf. Syst., Ghent Univ., Ghent, Belgium
  • fYear
    2012
  • fDate
    17-21 Sept. 2012
  • Firstpage
    213
  • Lastpage
    216
  • Abstract
    We present a very compact analog-to-digital convertor (ADC) for use as a standard cell. To achieve an inherent accuracy of at least 12-bits without trimming or calibration, extended counting A/D-conversion is used. Here, the circuit performs a conversion by passing through two modes of operation: first it works as a 1st-order incremental convertor and then it is reconfigured to operate as a conventional algorithmic converter. This way, we obtain a Nyquist-rate converter that requires only 1 operational amplifier and achieves 12-bit accuracy performance in 13 clock cycles with 9 bit capacitor matching. The circuit is designed in 0.18 μm CMOS with a thick oxide option. The resulting analog core occupies a chip area of only 0.011 mm2 and the complete digital control and reconstruction logic (including additional test features and storage registers) is 0.02 mm2. The analog blocks of the circuit consume 1.2mW and the digital 0.4mW. At a sample rate of 1 MS/s, the peak SNDR is 74.5dB and the dynamic range is 78dB, constant over the Nyquist band. The worst-case integral non-lineairity (INL) is within ±0.55 LSB.
  • Keywords
    CMOS analogue integrated circuits; analogue-digital conversion; capacitors; clocks; counting circuits; operational amplifiers; 1st-order incremental convertor; ADC; CMOS; INL; Nyquist band; Nyquist-rate A/D-converter; algorithmic converter; analog block; analog core; capacitor matching; chip area; circuit design; clock cycle; compact analog-to-digital convertor; counting A/D-conversion; digital control; noise figure 74.5 dB; noise figure 78 dB; operational amplifier; power 0.4 mW; power 1.2 mW; reconstruction logic; size 0.18 mum; standard cell; storage register; thick oxide option; word length 12 bit; word length 9 bit; worst-case integral nonlineairity; Accuracy; Capacitors; Clocks; Dynamic range; Noise; Silicon; Switches;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    ESSCIRC (ESSCIRC), 2012 Proceedings of the
  • Conference_Location
    Bordeaux
  • ISSN
    1930-8833
  • Print_ISBN
    978-1-4673-2212-6
  • Electronic_ISBN
    1930-8833
  • Type

    conf

  • DOI
    10.1109/ESSCIRC.2012.6341296
  • Filename
    6341296