Title :
A ring-VCO-based sub-sampling PLL CMOS circuit with −119 dBc/Hz phase noise and 0.73 ps jitter
Author :
Sogo, Kenta ; Toya, Akihiro ; Kikkawa, Takamaro
Author_Institution :
Res. Inst. for Nanodevice & Bio Syst., Hiroshima Univ., Higashi-hiroshima, Japan
Abstract :
This paper presents a ring-voltage-controlled-oscillator (ring-VCO)-based sub-sampling phase locked loop (PLL) CMOS circuit with low phase noise and low jitter. A 2.08 GHz PLL is designed and fabricated in 65 nm CMOS technology. The PLL consumes 20.4 mW while the in-band phase noise is -119.1 dBc/Hz at 1.4 MHz and the output jitter integrated from 1 kHz to 10 MHz is 0.73 ps (rms). The figure of merit (FOM) is -229.7 dB, which is the best data ever reported.
Keywords :
CMOS integrated circuits; jitter; phase locked loops; phase noise; voltage-controlled oscillators; CMOS technology; FOM; figure of merit; frequency 1 kHz to 10 MHz; frequency 1.4 MHz; jitter; phase noise; power 20.4 mW; ring-VCO-based subsampling PLL CMOS circuit; ring-voltage-controlled-oscillator; size 65 nm; subsampling phase locked loop CMOS circuit; CMOS integrated circuits; CMOS technology; Clocks; Jitter; Phase locked loops; Phase noise; Voltage-controlled oscillators;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341333
