Title :
A 2.9-mW 11-b 20-MS/s pipelined ADC with dual-mode-based digital background calibration
Author :
Sun, Nan ; Lee, Hae-Seung ; Ham, Donhee
Author_Institution :
Univ. of Texas at Austin, Austin, TX, USA
Abstract :
We report an 11-b 20-Ms/s pipelined ADC in 0.18-μm CMOS with a novel dual-mode-based digital background calibration method that altogether corrects errors caused by gain insufficiency, gain nonlinearity, and capacitor mismatches. The calibration enables an intentional use of low-gain single-stage op amps instead of conventional high-gain multi-stage op amps, with which we achieve a total ADC power dissipation of 2.9 mW and a short convergence time of 105. The calibration improves the SNDR from 45 dB to 60 dB, and the SFDR from 50 dB to 86 dB. The figure-of-merit is 174 fJ/conversion-step.
Keywords :
CMOS integrated circuits; analogue-digital conversion; calibration; capacitors; convergence; low-power electronics; operational amplifiers; ADC power dissipation; CMOS integrated circuit; capacitor mismatches; dual-mode-based digital background calibration; gain insufficiency; gain nonlinearity; high-gain multistage op amps; low-gain single-stage op amps; pipelined ADC; power 2.9 mW; short convergence time; size 0.18 mum; word length 11 bit; CMOS integrated circuits; Calibration; Capacitors; Charge transfer; Convergence; Gain; Operational amplifiers;
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
DOI :
10.1109/ESSCIRC.2012.6341337
