DocumentCode :
1980866
Title :
SLC: Split-control Level Converter for dense and stable wide-range voltage conversion
Author :
Kim, Yejoong ; Lee, Yoonmyung ; Sylvester, Dennis ; Blaauw, David
Author_Institution :
Dept. of Electr. Eng. & Comput. Sci., Univ. of Michigan, Ann Arbor, MI, USA
fYear :
2012
fDate :
17-21 Sept. 2012
Firstpage :
478
Lastpage :
481
Abstract :
Ultra-low voltage design makes signal level conversion a critical component in modern low power designs. This paper proposes a static level converter operating in the subthreshold regime, called SLC (Split-control Level Converter). Using a novel circuit structure, SLC effectively eliminates the high leakage and short circuit currents in previous approaches. Designed for 300mV to 2.5V conversion and fabricated in 130nm CMOS, measured results show 2.3×, 9.9×, and 5.9× improvements over conventional DCVS structures in delay, static power, and energy per transition, respectively. Even with the smallest area among wide-range level converters, it also has 5.2× smaller standard deviation in delay and only 5.6% change in FO4 delay with 10% VDDL drop, demonstrating robustness.
Keywords :
CMOS integrated circuits; low-power electronics; power convertors; short-circuit currents; CMOS process; DCVS structures; FO4 delay; SLC; circuit structure; low power designs; short circuit currents; size 130 nm; split-control level converter; stable wide-range voltage conversion; static level converter; ultralow voltage design; voltage 300 mV to 2.5 V; CMOS integrated circuits; Delay; Robustness; Synchronization; Temperature dependence; Temperature distribution; Temperature measurement;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
ESSCIRC (ESSCIRC), 2012 Proceedings of the
Conference_Location :
Bordeaux
ISSN :
1930-8833
Print_ISBN :
978-1-4673-2212-6
Electronic_ISBN :
1930-8833
Type :
conf
DOI :
10.1109/ESSCIRC.2012.6341359
Filename :
6341359
Link To Document :
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