Abstract :
The normal difficulties of reliability modeling, prediction, and verification of integrated circuits are complicated by the reliability requirements and erase/program methods of reprogrammable nonvolatile memories (RNVM). The additional reliability requirements are the endurance and data retention parameters. The erase/program methods involve the generation and application of high voltage signals that can cause various “disturb” phenomena, in conjunction with the normal reliability concerns associated with electric field strength. This paper provides a brief overview of modeling, prediction, and verification methods for RNVM, concentrating on the unique aspects of RNVM. Some reference is made to standard methods, where appropriate. Additional information can be found in standard texts on reliability, CMOS circuitry, the IEEE Floating Gate Standard, various IEEE papers, various JEDEC test methods, and books on nonvolatile memory
Keywords :
EPROM; integrated circuit modelling; integrated circuit reliability; integrated circuit testing; integrated memory circuits; programmable circuits; standards; CMOS circuitry; EEPROM; IC reliability; IEEE Floating Gate Standard; JEDEC test methods; RNVM; data retention parameters; disturb phenomena; electric field strength; endurance parameters; erase/program methods; high voltage signals; integrated circuits; nonvolatile memory; reliability modeling; reliability prediction; reliability requirements; reliability verification; reprogrammable nonvolatile memories; standard methods; Books; CMOS memory circuits; Circuit testing; Integrated circuit modeling; Integrated circuit reliability; Nonvolatile memory; Predictive models; Semiconductor device modeling; Signal generators; Voltage;
