Circuits and algorithms for adaptive neuro-fuzzy analog chips

This paper presents adaptive circuit blocks and related learning algorithms to design neuro/fuzzy inference systems using analog integrated circuits in CMOS, standard VLSI technologies. Proposed circuit building blocks are arranged in a layered architecture composed of five layers: fuzzification, T-norm, normalization, consequent, and output. Inference is performed using Takagi and Sugeno´s if-then rules, particularly where the rule´s output contain only a constant term-a singleton. The proposed learning scheme uses weight perturbation for the fuzzification layer and outstar for the output layer. A three-input, four-rule controller has been designed for demonstration purposes in a 1.6 μm CMOS single-poly, double-metal technology. Its operation speed is in the range of 5MFlips with systematic errors around 1%