Title :
System-level design of IEEE1394 bus segment bridge
Author :
Yamamoto, Hirofumi ; Chikamura, Keishi ; Shigiya, Atsuhito ; Tsujino, Kosuke ; Izumi, Tomonori ; Onoye, Takao ; Ura, Akam
Author_Institution :
Dept. Commun. & Comput. Eng., Kyoto Univ., Japan
Abstract :
A system simulation environment is constructed dedicatedly for IEEE1394 high-speed digital communication. In this environment, various network transactions inherent in communication systems are taken into account for system simulation, which is indispensable to enable IP (Intellectual Property)-based design of the systems. By using the proposed environment, system-level design of IEEE1394 link layer controller and bus segment bridge is achieved with great ability of network transactions as well as connectivities with physical layer chips. Functionalities of the designed bus segment bridge has been verified according to its FPGA implementation.
Keywords :
IEEE standards; hardware-software codesign; system buses; HW/SW co-simulation; IEEE1394; bus segment bridge; digital communication; link layer controller; system-level design; Bridges; Control systems; Discrete event simulation; Field programmable gate arrays; Hardware design languages; Network interfaces; Physical layer; Protocols; System-level design; System-on-a-chip;
Conference_Titel :
System Synthesis, 2002. 15th International Symposium on
Conference_Location :
Kyoto, Japan
Print_ISBN :
1-58113-576-9