A High-Rate, Low-Power, ASIC Speech Decoder Using Finite State Transducers

The use of Finite State Transducers in speech recognition has been increasing in recent years. Their application in speech decoding allows for a tradeoff between larger memory requirements and less run-time computation. We believe that this paradigm is especially well suited for a highspeed, energy-efficient hardware solution where customized caching, reduced bit widths, and prefetching can be used to mitigate the effect of the increased model size. We present a virtual silicon prototype for a novel hardware architecture that, using these optimizations and running at 556MHz, is capable of performing recognition on the Wall Street Journal 60K- word speech model with 92.3 percent accuracy a speed 127 times faster than real time, while consuming less than 0.5 watts.