Title :
A dense 45nm half-differential SRAM with lower minimum operating voltage
Author :
Chen, Gregory ; Wieckowski, Michael ; Kim, Daeyeon ; Blaauw, David ; Sylvester, Dennis
Author_Institution :
Univ. of Michigan, Ann Arbor, MI, USA
Abstract :
We present a 45 nm half-differential 6T SRAM (HD-SRAM) with differential write and single-ended read, enabling asymmetric sizing and VTH selection. The HD-SRAM bitcell uses SRAM physical design rules to achieve the same area as a commercial differential 6T SRAM (D-SRAM). We record measurements from 80 32 kb SRAM arrays. HD-SRAM is 18% lower energy and 14% lower leakage than D-SRAM. It has a 72 mV-lower VMIN, demonstrating higher stability.
Keywords :
SRAM chips; write-once storage; HD-SRAM; SRAM arrays; asymmetric sizing; differential write; half-differential 6T SRAM; lower minimum operating voltage; single-ended read; storage capacity 2560 Kbit; Circuit stability; Partial discharges; Random access memory; Robustness; Semiconductor device measurement; Stability criteria;
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
DOI :
10.1109/ISCAS.2011.5937500
