DocumentCode :
1985264
Title :
A novel SST transmitter with mutually decoupled impedance self-calibration and equalization
Author :
Chen, Shuai ; Yang, LiQiong ; Jing, Hua ; Zhang, Feng ; Gao, Zhuo
Author_Institution :
Inst. of Comput. Technol., Beijing, China
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
173
Lastpage :
176
Abstract :
A low power source-synchronous source-series- terminated (SST) transmitter (Tx) in 65 nm CMOS technology is presented. The Tx, comprised of nine data/control channels, a forwarded-clock channel and one PLL, merely dissipates 26.2 mW/channel while exhibiting a 750 mV differential eye height at 6.4 Gbps. The SST drivers can save ¾ output stage power of CML ones, and moreover, the proposed novel topology can independently control impedance self-calibration and equalization. To implement half-rate architecture, the PVT- tolerant PLL provides a pair of quadrature clocks with 2.5 ps rms cycle to cycle jitters running at 3.2 GHz.
Keywords :
CMOS integrated circuits; equalisers; jitter; phase locked loops; transmitters; CMOS technology; PVT-tolerant PLL; SST transmitter; cycle to cycle jitters; equalization; forwarded-clock channel; frequency 3.2 GHz; half-rate architecture; low power source-synchronous source-series-terminated transmitter; mutually decoupled impedance self-calibration; quadrature clocks; size 65 nm; Calibration; Clocks; Computer architecture; Driver circuits; Impedance; Phase locked loops; Transmitters;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5937529
Filename :
5937529
Link To Document :
بازگشت