Receiver of L-DACS1 Physical Layer System

According to the proposal of L-DACS1, we build the model of the receiver of the physical layer of the L-DACS1 system, using verilog HDL and DSP programming language. Timing synchronization module, which is used to locate the signals with noises accurately, is programmed in verilog HDL, considering the special structure of the time domain representation of synchronization symbols. The module of channel estimating and equalizing process the data using DSP chips, so than we can avoid errors brought by fixed algorithms and reduce the work of FPGA effectively at the same time. The result shows that the receiver can ensure a good use of the resources on chips and realize accurate and continuous work, using FPGA and DSP.