A structured design for test methodology

Author

Venkat, K.

Author_Institution

Silicon Graphics Inc., Moutain View, CA, USA

fYear

1993

fDate

6-8 April 1993

Firstpage

333

Lastpage

336

Abstract

Presents a case study of a structured design for test (DFT) methodology that was formulated for a major system design project consisting of 11 complex ASICs. The methodology includes full scan for chip test, and an optimized boundary scan for board test. The paper discusses details of the ASIC designs and technology, the DFT methodology, the design of test logic, ATPG tool selection, development of in-house tools, and integration of DFT into the overall design flow. This project has demonstrated that DFT can be considered early in the design and integrated efficiently into the design flow.<>

Keywords

application specific integrated circuits; automatic testing; boundary scan testing; design for testability; logic CAD; logic testing; ATPG tool selection; board test; chip test; complex ASICs; design flow; full scan; in-house tools; optimized boundary scan; structured design for test methodology; system design project; test logic; Application specific integrated circuits; Assembly systems; Automatic test pattern generation; Design for testability; Design methodology; Graphics; Logic design; Logic testing; Silicon; System testing;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Test Symposium, 1993. Digest of Papers., Eleventh Annual 1993 IEEE

Conference_Location

Atlantic City, NJ, USA

Print_ISBN

0-8186-3830-3

Type

conf

DOI

10.1109/VTEST.1993.313372

Filename

313372