An FPGA-based irrational decimator for digital receivers

An efficient FPGA implementation of an irrational CIC filter for decimation in digital receivers is presented in this paper. The proposed approach employs dual-port RAMs prevailing in almost all recent FPGAs, favorably decreases the number of used slices and increases the operating frequency. The circuit has been implemented on a Xilinx Virtex-II Pro XC2VP50-6 and has been used in some digital demodulators successfully. The decimator can properly apply a wide range of decimation factors from 1 to some hundreds and can work in frequencies up to 150 MHz in the mentioned FPGA.