DocumentCode :
1987456
Title :
DET FF topologies: A detailed investigation in the energy-delay-area domain
Author :
Alioto, Massimo ; Consoli, Elio ; Palumbo, Gaetano
Author_Institution :
Dept. of Inf. Eng., Univ. of Siena, Siena, Italy
fYear :
2011
fDate :
15-18 May 2011
Firstpage :
563
Lastpage :
566
Abstract :
In this paper, a comparison of representative Dual-Edge-Triggered flip-flop topologies is carried out in a 65-nm CMOS technology. The energy efficiency is analyzed together with other aspects, such as the area-delay tradeoff, leakage and clock-load, which are typically neglected in previous works. The investigation highlights the impact of effects that become dominant in nanometer technologies (e.g., local interconnects, leakage) and allows for identifying the most effective FFs belonging to the DET class, as well as to evaluate the suitability of DET topologies for real applications.
Keywords :
CMOS digital integrated circuits; flip-flops; network topology; CMOS technology; DET FF topology; area-delay tradeoff; dual-edge-triggered flip-flop topology; energy efficiency; energy-delay-area domain; leakage-clock-load; nanometer technology; size 65 nm; Capacitance; Clocks; Delay; Energy efficiency; Flip-flops; Layout; Topology;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location :
Rio de Janeiro
ISSN :
0271-4302
Print_ISBN :
978-1-4244-9473-6
Electronic_ISBN :
0271-4302
Type :
conf
DOI :
10.1109/ISCAS.2011.5937627
Filename :
5937627
Link To Document :
بازگشت