RF noise modelling of 0.25 /spl mu/m CMOS and low power LNAs

A prototype 0.5 /spl mu/m CMOS LNA with a noise figure of 2.2 dB and a gain of 16.9 dB at 900 MHz at a power consumption of 1.8 mW is reported. This result, and the noise figures obtained on 0.25 /spl mu/m CMOS, are reproduced by simulations, confirming that RF noise modeling can be accurately performed using our public domain MOS Model 9. Simulations are presented for similar LNAs realized in standard CMOS processes with gate dimensions down to 0.13 /spl mu/m. Provided high Q matching circuitry is used, for the latter gate length a noise figure of only 1.1 dB and 27 dB gain at 1800 MHz, at a minimal power consumption of only 0.2 mW, is predicted.