DocumentCode :
1987916
Title :
A Compact Model for Reliability Simulation of Deep-Submicron MOS Devices and Circuits
Author :
Cui, Zhi ; Liou, Juin J.
Author_Institution :
Department of Electrical and Computer Engineering, University of Central, Florida, Orlando, Florida, 32816 USA, Fax: 407-823-5835
fYear :
2005
fDate :
19-21 Dec. 2005
Firstpage :
391
Lastpage :
396
Abstract :
Continuing down scaling in CMOS technology has resulted in an increasing and urgent need for a Spice-like reliability model that is capable of predicting the long-term degradation of MOS devices and ICs. In this paper, we develop such a model based on the industry standard BSIM3 model and empirical degradation expressions for the threshold voltage and mobility of MOSFETs. The model is implemented in Cadence Spectre via Verilog-A, and measured data obtained from devices fabricated from the 0.18-μm CMOS technology have been included in support of the model development.
Keywords :
CMOS technology; Circuit simulation; Degradation; Hardware design languages; MOS devices; MOSFETs; Predictive models; Semiconductor device modeling; Standards development; Threshold voltage;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Electron Devices and Solid-State Circuits, 2005 IEEE Conference on
Print_ISBN :
0-7803-9339-2
Type :
conf
DOI :
10.1109/EDSSC.2005.1635289
Filename :
1635289
Link To Document :
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