DocumentCode :
1989587
Title :
The novel stress simulation method for contemporary DRAM capacitor arrays
Author :
Kyu-Baik Chang ; Yun Young Kim ; Jiwoong Sue ; Hojoon Lee ; Won-young Chung ; Keun-Ho Lee ; Young-Kwan Park ; EunSeung Jung ; Ilsub Chung
Author_Institution :
Semicond. R&D Center, Samsung Electron. Co., Ltd., Hwasung, South Korea
fYear :
2013
fDate :
3-5 Sept. 2013
Firstpage :
424
Lastpage :
427
Abstract :
The increasing of aspect ratio in DRAM capacitors causes structural instabilities and device failures as the generation evolves. Conventionally, two-dimensional and three-dimensional models are used to solve these problems by optimizing thin film thickness, material properties and structure parameters; however, it is not enough to analyze the latest failures associated with large-scale DRAM capacitor arrays. Therefore, beam-shell model based on classical beam and shell theories is developed in this study to simulate diverse failures. It enables us to solve multiple failure modes concurrently such as supporter crack, capacitor bending, and storage-poly fracture.
Keywords :
DRAM chips; capacitors; semiconductor device models; thin film devices; aspect ratio; beam-shell model; capacitor bending; classical beam; contemporary DRAM capacitor arrays; device failures; diverse failures; large-scale DRAM capacitor arrays; material properties; shell theories; storage-poly fracture; stress simulation method; structural instabilities; structure parameters; thin film thickness; Analytical models; Capacitors; Fabrication; Materials; Random access memory; Solid modeling; Stress; beam-shell model; capacitor stress; large-scale simulation;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Simulation of Semiconductor Processes and Devices (SISPAD), 2013 International Conference on
Conference_Location :
Glasgow
ISSN :
1946-1569
Print_ISBN :
978-1-4673-5733-3
Type :
conf
DOI :
10.1109/SISPAD.2013.6650665
Filename :
6650665
Link To Document :
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