An improved model for delay/energy estimation in near-threshold flip-flops

Near-threshold (NT) FFs, which operate from a supply voltage close to the transistor threshold voltage, are considered as a good alternative for portable applications, where low power dissipation with reasonable performance is the main demand. This paper presents an improved model for delay/energy estimation of the NT FFs. The proposed model, based on the EKV current and alpha power law models, improves the existing model by taking into account the rise and fall times of all internal nodes of the FF. The fitting parameters that are required for the model development were extracted from measurements of a test chip that was fabricated in a standard CMOS low power 80nm process. We show how the proposed model can be utilized for NT Master-Slave FF delay and energy estimation, showing an improvement of up to xlOO in the precision of calculations compared to the existing model.