A Leakage Power Estimation Method for Standard Cell Based Design

The leakage current grows dramatically as the feature size of CMOS circuit scaling down. The estimation of leakage power consumption of CMOS digital circuits can help to find the hot point of the design and evaluate different optimization schemes. This paper introduced a leakage power estimation method compatible with traditional dynamic power estimation flow for standard cell based CMOS design. This method uses node occurrence probability (NOP) information to indicate the state of standard cells. When leakage power look up table was pre-characterized for standard cells, the NOP based method can evaluate the leakage power of standard cell based circuit with the accuracy of HSpice, but the estimation speed will be 100 times faster than HSpice.