Reduced overhead by partitioning of a circular-shift PLAs

A design method for a built-in self-test PLA (programmable logic array) is investigated. This method is referred to as circular-shift PLA (CS-PLA). The basic mechanism of the CS-PLA technique is to add dynamic shift registers to the original PLA in order to control each product line and each complementary pair of bit lines. During test mode operation the contents of the registers are initialized and subsequently advanced in such a way as to select one pair of bit lines and only one product term line at any time. The authors propose to group the product lines that have no common output line at OR-plane. In this case, the area overhead associated with the CS-PLA concept can be reduced. The characteristic of the area overhead versus PLA size is given