A 400 MHz delta-sigma modulator for bandpass IF digitization around 100 MHz with excess loop delay compensation

The past few years has seen a tremendous amount of work being published in the area of continuous-time delta-sigma ADC designs with various compensation techniques to counter its susceptibility to non-idealities like clock jitter and excess loop delay, to name a few. The focus of this paper is the design of a tunable continuous time bandpass delta-sigma modulator that utilizes an excess loop delay compensation technique proposed to optimize the SNR of the modulator, besides preserving its stability by incorporating a full clock cycle delay. An improved, low noise, compact gyrator-C structure is proposed to obtain a high-Q bandpass filter subsequently used in the design of a second-order bandpass delta-sigma modulator clocked at 400 MHz for direct conversion of narrow band signals around 100 MHz. The proposed structure eliminates the need of a capacitor bank/array for the coarse tuning of the modulator since this structure enables coarse tuning in the range of 80 to 120 MHz and fine tuning of 5 MHz above or below the centre frequency. This modulator has been implemented in AMI 0.5μ CMOS process and achieves an SNR of 46 dB over a bandwidth of 1 MHz, calculated from post-layout simulations. The power consumption of this design is 49 mW at a supply of 3V.