DocumentCode
1992005
Title
Automatic signal net-matching for VLSI layout design
Author
Xiong, Xiao-Ming ; Green, Dan ; Hardin, John ; Riedel, Lawrence
Author_Institution
Appl. Micro Circuits Corp., San Diego, CA, USA
fYear
1989
fDate
2-4 Oct 1989
Firstpage
524
Lastpage
527
Abstract
In high-speed VLSI design, the matching of signal net lengths is often critical to the proper performance of a circuit. Given a design which specifies groups of signal nets to be matched, a physical layout must be generated which conforms to these constraints. Different aspects of the problem in VLSI design layout are investigated, and the approaches used to automate the process are presented
Keywords
VLSI; circuit layout CAD; VLSI layout design; automate; automatic signal net-matching; circuit performance; physical layout; signal net lengths; Circuit optimization; Circuit synthesis; Clocks; Delay effects; Design optimization; Joining processes; Routing; Signal design; Very large scale integration; Wire;
fLanguage
English
Publisher
ieee
Conference_Titel
Computer Design: VLSI in Computers and Processors, 1989. ICCD '89. Proceedings., 1989 IEEE International Conference on
Conference_Location
Cambridge, MA
Print_ISBN
0-8186-1971-6
Type
conf
DOI
10.1109/ICCD.1989.63421
Filename
63421
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