DocumentCode
1992275
Title
Early case splitting and false path detection to improve high level ATPG techniques
Author
Alizadeh, Bijan ; Fujita, Masahiro
Author_Institution
Electr. & Comput. Eng. Dept., Univ. of Tehran, Tehran, Iran
fYear
2011
fDate
15-18 May 2011
Firstpage
1463
Lastpage
1466
Abstract
Early generation of effective high level test patterns can significantly reduce Automatic Test Pattern Generation (ATPG) efforts in gate level. This paper proposes an ATPG methodology targeting non-scan designs. Although our methodology checks all execution paths, a decision procedure is applied to detect the false paths very early and split the cases before generating high level test patterns. Experimental results show robustness and reliability of our method compared to FlexTest as a commercial gate level ATPG tool.
Keywords
automatic test pattern generation; logic design; logic testing; automatic test pattern generation; early case splitting; false path detection; gate level ATPG tool; high level ATPG techniques; high level test pattern generation; nonscan designs; Automatic test pattern generation; Benchmark testing; Circuit faults; Integrated circuit modeling; Logic gates; Polynomials; Sequential circuits;
fLanguage
English
Publisher
ieee
Conference_Titel
Circuits and Systems (ISCAS), 2011 IEEE International Symposium on
Conference_Location
Rio de Janeiro
ISSN
0271-4302
Print_ISBN
978-1-4244-9473-6
Electronic_ISBN
0271-4302
Type
conf
DOI
10.1109/ISCAS.2011.5937850
Filename
5937850
Link To Document