Signature-based Microprocessor Power Modeling for Rapid System-level Design Space Exploration

This paper presents a technique for high-level power estimation of microprocessors. The technique, which is based on abstract execution profiles called ´event signatures´, operates at a higher level of abstraction than commonly-used instruction-level power simulators and should thus be capable of achieving good evaluation performance. We have compared our power estimation results to those from the instruction-level simulator Wattch. In these experiments, we demonstrate that with a good underlying power model, the signature-based power modeling technique can yield accurate estimations (a mean error of 5.5 percent compared to Wattch in our experiments). At the same time, the power estimations based on our event signature technique are at least an order of magnitude faster than with Wattch.