• DocumentCode
    1994404
  • Title

    A Flexible Memory Controller Supporting Deep Belief Networks with Fixed-Point Arithmetic

  • Author

    JingFei Jiang ; Rongdong Hu ; Lujan, Mikel

  • Author_Institution
    Sch. of Comput. Sci., Nat. Univ. of Defense Technol., Changsha, China
  • fYear
    2013
  • fDate
    20-24 May 2013
  • Firstpage
    144
  • Lastpage
    152
  • Abstract
    Deep Belief Networks (DBNs) are state-of-art Machine Learning techniques and one of the most important unsupervised learning algorithms. Training DBNs is computationally intensive which naturally leads to investigate FPGA acceleration. Fixed-point arithmetic can have an important influence on the execution time and prediction accuracy of a DBN. Previous studies have focused only on customized DBN accelerators with a fixed data-width. Our results experiments demonstrate that supporting various data-widths in different DBN configurations and application environments does make sense for achieving acceptable performance. From this we conclude that a DBN accelerator should support various data-widths rather than the fixed one as done in previous work. The processing performance of DBN accelerators in FPGA is almost always constrained not by the capacity of the processing units, but by their on-chip RAM capacity and speed. We propose an efficient memory controller for DBN accelerators, which shows that supporting various data-widths is not as difficult as it may sound. The cost is only little in hardware terms and does not affect the critical path. We have designed a tool to help users reconfiguring the memory controller with arbitrary data-width flexibly.
  • Keywords
    belief networks; field programmable gate arrays; storage management chips; DBN accelerator; FPGA acceleration; deep belief networks; fixed data-width; fixed-point arithmetic; flexible memory controller; on-chip RAM capacity; state-of-art machine learning techniques; unsupervised learning algorithms; Approximation methods; Educational institutions; Field programmable gate arrays; Hardware; Random access memory; System-on-chip; Training; Deep Belief Network; fixed-point arithmetic; memory controller;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Parallel and Distributed Processing Symposium Workshops & PhD Forum (IPDPSW), 2013 IEEE 27th International
  • Conference_Location
    Cambridge, MA
  • Print_ISBN
    978-0-7695-4979-8
  • Type

    conf

  • DOI
    10.1109/IPDPSW.2013.98
  • Filename
    6650881