Thermal Aware Module Placement for Heterogeneous 3D-IC Based FPGAs

In this paper we introduce a module placer targeting 3D-IC FPGA based systems. 3D-IC devices are devices consisting of several stacked ICs contained within one package. These devices present new challenges, but also exacerbate challenges identified in current 2D-IC FPGA devices. Thus, module placement on 3D-IC based FPGA devices require improvements over traditional 2D-IC FPGA models. We present an improved module placer based on an existing heterogeneous module placer. The module placer targets systems designed with a component-based flow and systems using partial run-time reconfiguration using relocatable modules (IP-cores). We have extended the module placer to support the thermal footprint of the modules and the ability to compute a feasible placement in a stack of FPGA ICs. The thermal footprint of the modules is taken into account when computing feasible placement positions. In addition, we model systems consisting of a combination of an FPGA IC and other ICs. The target is to reduce the peak temperature and hotspots (i.e. by avoiding clustering of hot modules). We have compared peak temperature for thermal constrained modules to the peak temperature when placing modules without thermal constraints. Experiments undertaken show a reduction of peak temperature of up to 10°C. The improvement is possible with thermal aware module placement.