Reconfigurable clock polarity assignment for peak current reduction of clock-gated circuits

This paper presents a novel clock polarity assignment method to reduce the peak current on the vdd/gnd rails of a clock-gated integrated circuit. The proposed method inserts XOR gates at one level of the clock tree to facilitate the polarity assignment with limited skew degradation. The polarity of clock buffers are configured during runtime such that a maximal peak current reduction is obtained after clock gating. The method is integrated into an industrial design flow to study the practicality. Experimental results show that the worst case peak current on a clock tree can be reduced by 33.3% and 33.9% by inserting XOR gates at the sink level and non-sink level of the clock tree, respectively. Additional 12.8% and 12.9% reductions in the worst case peak current for a clock tree with XOR gates inserted at the sink and non-sink level, respectively, can be achieved by reconfiguring the polarity assignment during runtime based on the clock gating information.