A 0.7-V 100-µW audio delta-sigma modulator with 92-dB DR in 0.13-µm CMOS

Author

Yang, Zhenglin ; Yao, Libin ; Lian, Yong

Author_Institution

Dept. of Electr. & Comput. Eng., Nat. Univ. of Singapore, Singapore, Singapore

fYear

2011

fDate

15-18 May 2011

Firstpage

2011

Lastpage

2014

Abstract

A low-voltage fourth-order audio ΔΣ modulator is designed with a single-loop single-bit feedforward structure. A 2- tap FIR filter is inserted in the feedback loop to effectively attenuate the high frequency quantization noise, resulting 22% reduction in the maximum integration step of the first integrator and relaxing the slew rate requirement for the OTA to 9.5 V/μsec (diff). The summation of feedforward paths is embedded in a multi-input quantizer to minimize power and area. Implemented in a 0.13-μm CMOS technology and clocked at 4 MHz, the modulator achieves 87.0 dB SNDR and 91.8 dB DR for a 20-kHz signal bandwidth while consuming 99.7 μW from a 0.7-V supply.

Keywords

CMOS analogue integrated circuits; FIR filters; delta-sigma modulation; integrated circuit noise; operational amplifiers; 2-tap FIR filter; CMOS technology; OTA; bandwidth 20 kHz; feedback loop; feedforward path summation; frequency 4 MHz; high frequency quantization noise; low-voltage fourth-order audio ΔΣ modulator; low-voltage fourth-order audio delta-sigma modulator; maximum integration step; multiinput quantizer; noise figure 87 dB; noise figure 91.8 dB; noise figure 92 dB; power 100 muW; signal bandwidth; single-loop single-bit feedforward structure; size 0.13 mum; slew rate requirement; voltage 0.7 V; Feedforward neural networks; Finite impulse response filter; Modulation; Quantization; Semiconductor device measurement; Signal to noise ratio;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems (ISCAS), 2011 IEEE International Symposium on

Conference_Location

Rio de Janeiro

ISSN

0271-4302

Print_ISBN

978-1-4244-9473-6

Electronic_ISBN

0271-4302

Type

conf

DOI

10.1109/ISCAS.2011.5937990

Filename

5937990