The design of a six-digit digital clock with a four-digit seven-segment display module

This paper presents a field programmable gate array (FPGA) prototype of a 6-digit digital clock displaying time on a four-digit seven-segment LED module. The design of the digital clock is based on the Very High Speed Integrated Circuit Hardware Description Language (VHDL) hardware description language, synthesized by the Xilinx Synthesis Technology (XST) synthesizer, and implemented per Spatan-3 xc3s200-4ft256 FPGA chip. The circuit was tested to run on the Spartan-3 Starter Board. The resources utilization after the Integrated Software Environment (ISE) design flow is reported. Two accuracy test results are provided, the possible error sources are discussed and one possible approach to identify the error source is offered. The design itself suggests a common time tool for many digital applications.