Adjustable input Self-Strobed Delay Line ADC intended to implantable devices

This paper concerns the design of a Self-Strobed Delay Line Analog-to-Digital Converter (SSDL ADC) which is dedicated to digitally controlled Switched Mode Power Supply (SMPS) in implantable devices. The proposed windowed-based ADC can be adapted for different input signal levels. A new single slow delay cell is used to reduce power consumption, silicon area and hardware complexity. In implantable devices, further to low-power consumption and small area, the ADC is required to operate in continuously decreasing power supply. Consequently, a new current sink circuit is utilized to eleminate the need to redesign its controller if the characteristics of the supply devices change. The ADC is designed in AMS 0.35 μm CMOS process and it c an operate at high switching frequency. Spectre simulations of this ADC show a current consumption as low as 10μA/MHz, and the circuit can provide a wide operating range from zero to 1.5 V with quantization steps smaller than 1% of V_ref.